The present disclosure relates to forming lines within integrated circuit devices, and more specifically to structures and processes related to the formation of uniform line ends.
Many different devices within integrated circuits are insulated from one another or are electrically connected to one another using linear structures, such as insulating regions or conductive lines. For purposes herein, linear structures are those that have a length dimension that is many times greater than (e.g., 10×, 100×, 1000×) the width dimension, and such structures are generally formed to include one or more sections that extend along a single straight line.
As devices are made smaller and smaller (device scaling) it is useful to have as little excess area surrounding structures, so as to utilize the available real estate of the integrated circuit device to the maximum extent possible. Thus, the dimensions of various devices should be tightly controlled so as to use the available real estate effectively. One concept that is directed toward achieving such an efficient utilization of integrated circuit real estate is critical dimension uniformity (CDU).
With respect to conductive lines, in order to achieve critical dimension uniformity, some processes utilize masks to cut or trim the conductive lines (cutmask for polysilicon conductor; CT for PC); utilize self-aligned double patterning processes (SADP); or utilize other resolution enhanced techniques (or resolution enhanced optical lithography technology; RET). For example, with RET, illuminator parameters or settings can be varied, such as illuminator source shape (e.g., annular source shape, dipole source shape, quadrupole source shape), orientation of the poles, radius, and pole angle. Further, mask or reticle parameters that can be varied with RET include mask type (e.g., binary, phase shift mask (PSM), attenuated PSM) and mask transmission.